1. Field of the Invention
The present invention generally relates to an improved method and apparatus for computer-aided integrated circuit (IC) design automation, and more specifically to IC physical design (PD) and electrical simulation. In particular, the present invention provides a method and apparatus to partition the physical design of an IC so as to divide the host computer resource demand of file space, memory and computation needed for IC electrical simulation.
2. Description of the Related Art
Conventional ICs use three signal xe2x80x9ctypesxe2x80x9d, namely, power signals, clock signals, and data/control signals. These signals arrive at the IC signal interface from external sourcesxe2x80x94the power supply, clock, memory/file and external ICs. Signals are then distributed by their respective xe2x80x9cgridsxe2x80x9d to their semiconductor transistors where the arithmetic/logic functions are performed; and then are returned to the IC signal interface by the appropriate signal grid.
Signal voltages are xe2x80x9cvoltage dividedxe2x80x9d from their initial xe2x80x9chighxe2x80x9d potential at the IC signal interface to a lower potential at the IC transistors. These signals may then again be divided in potential from that at the IC transistors to a final low potential at the IC signal interface.
These three grids are realized by the IC fabrication process as a series of conductive xe2x80x9cmeshxe2x80x9d levels and interconnecting xe2x80x9cviaxe2x80x9d levels that are physically superimposed within the IC but electrically insulated. The metalization process creates a three-dimensional structure where the mesh levels are a laminate of x-y (i.e., horizontal) planes, stacked in the z (i.e., vertical) plane and connected by the via levels. A contemporary microprocessor IC may have six to eight mesh levels and as many via levels.
For example, FIG. 1 shows a first mesh level 10 and a second mesh level 12. Aluminum or aluminum/copper alloy conductors may form the mesh levels 10, 12 and the via 20. The mesh levels 10, 12 and the via 20 are embedded in an insulator such as silicon dioxide 14. The via metalization is preferably formed by etching an opening in the silicon oxide 14, filling the hole with metal such as aluminum and then depositing the next mesh level over the via 20.
The signal grids may be described by a physical design (PD) database. The physical design database is a graphics description of the integrated circuit and includes graphic xe2x80x9cshapesxe2x80x9d such as rectangles and polygons with physical dimensions and geometries that are defined by the technology groundrules of the IC fabrication process. Shapes can be of two forms: xe2x80x9crealxe2x80x9d shapes that are translated into the fabrication process to direct the IC fabrication process, or xe2x80x9cattributexe2x80x9d shapes that describe the IC physical design but are unnecessary for the fabrication process. In other words, the graphics description represents the three-dimensional integrated circuit and includes all information necessary to build an IC.
In addition to representing the physical design of an IC, the physical design database can also be used to formulate an electrical network model of the IC. For example, FIG. 1 also shows electrical resistors 22 associated with the mesh levels 10, 12 and the via 20. The connection points of the resistors 22 are commonly referred to as nodes 24. The nodes 24 correspond to the physical shapes that comprise the mesh levels 10, 12 and the via 20 of the signal grids. Accordingly, the three-dimensional physical location of the nodes 24 is known based on the graphics description. The nodes 24 are the points at which the node voltages are determined by electrical simulation.
The process of translating the graphics description of the integrated circuit into an electrical simulation consists of isolating shapes of interest from the complete IC physical design. This is referred to as shapes extraction. So, for example, if the electrical simulation involves the IC power grid, then the shapes of the power grid are extracted from the total physical design IC. Then, using well known software programs such as SPICE and ASTAP, the physical shapes of the items of interest are converted into electrical components such as resistors, capacitors, inductors and transistors. For example, a rectangular shape that appears in a signal mesh may be translated into a resistor, with its nodes associated with the ends of the rectangle. From this shapes extraction, a netlist is produced that describes the circuit of interest using an interconnected set of electrical components. As is well known, a netlist is a description of element values (such as resistors, capacitors, inductors, current sources and voltage sources) and their interconnected relationship. An example of a netlist may be:
Res1, Axe2x88x92B=7.2
Res2, Bxe2x88x92C=2.1
J1, Cxe2x88x92A=1.6.
A contemporary microprocessor (or workstation) may have on the order of 50 million resistors in its power grid thereby leaving an extremely lengthy and sometimes impossible computation task.
Subsequently, a workstation applies an electrical simulation to the netlist.
As is known in the art, this involves the generation and solution of the matrix equation
Gv=ixe2x80x83xe2x80x83(1)
where the nodes of G correspond to values and interconnections of the netlist. Matrix equation (1) is derived from Ohm""s Law, namely V=iR.
A contemporary microprocessor (or workstation) can have on the order of 20 million nodes for its power grid, thereby leaving a rather lengthy and sometimes impossible computation task to solve the matrix equation (1).
Furthermore, integrated circuits (ICs) continue to increase in functionality and physical complexity. This significantly increases the design automation (DA) of the ICs. That is, the amount of data that needs to be computed is too large to be handled by one workstation. This requires more host computer resource than is available by conventional workstations. For example, a typical power signal for today""s IC is described by three gigabytes of netlist description and cannot be solved by conventional xe2x80x9cunixe2x80x9d processing. As explained in greater detail below, this problem has been solved in 30 minutes using the inventive approach.
In view of the foregoing and other problems of the conventional methods, it is, therefore, an object of the present invention to provide a method of designing an integrated circuit. The method may include receiving a graphical description of the integrated circuit, extracting shapes relating to a specific circuit function (such as power) from the graphical description of the integrated circuit and partitioning the extracted shapes into a plurality of segments. The method may further include forming an electrical representation of the integrated circuit for each of the plurality of segments and solving a matrix equation of Gv=i, where G relates to resistance, i relates to current and v relates to voltage, for each of the plurality of segments based on that electrical representation.
Partitioning the extracted shapes may include locating seams within the extracted shapes where each seam crosses a mesh line defined by the extracted shapes of the integrated circuit. The partitioning may also include creating stitches within the extracted shapes and identifying stitch nodes at areas where seams cross mesh lines. To solve the matrix equation, the method may include determining a voltage at each stitch node.
The electrical representation may further include a plurality of resistors that connect at each stitch node. The matrix equation may be solved by forming a matrix representation of each segment based on the electrical representation for that respective segment and determining a voltage at each stitch node for each respective segment.
The method may further include exchanging the determined stitch node voltages between adjacent segments, computing a new current for each segment, determining a new voltage at each stitch node for each respective segment using the new current and determining whether the new voltage at each stitch node is within a predetermined tolerance.
The matrix equation may be solved to determine a voltage at specific locations of the integrated circuit. The method may further include exchanging voltages between adjacent segments and performing an iterative process until the respective voltages are within a predetermined tolerance.
Other objects, advantages and salient features of the invention will become apparent from the following detailed description taken in conjunction with the annexed drawings, which disclose preferred embodiments of the invention.